פסיקות מערכות ובקרים. Why are interrupts important. The INT and IRET instructions. Saul Coval Computer Systems 1.

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PIC - /Jan/00 מנהל התקנים DMA Introduction to Systems Programming מבוא לתכנות מערכות Device Manager גישה יש ירה לז י כר ו ן פסיקות קלט פלט Input-Output Devices, Controllers, and I/O Architectures

controller Message to application Application OpSys Special memory location M Interrupt CPU Decides which app (window) was accessed sends a message to that window Adds letter M to Video RAM Adds

) Interrupts help peripherals talk to your microprocessor Interrupts help you measure time and control the timing of certain tasks in your microprocessors Slide Slide Interrupts from a pedagogical

multiple interrupts are serviced at the same time Preemptability and priorities, how can a low prioritytask be preempted by a high-priority task Scheduling: how can we assure that both low and

1 PIC - /Jan/00 מנהל התקנים DMA Introduction to Systems Programming מבוא לתכנות מערכות Device Manager גישה יש ירה לז י כר ו ן פסיקות קלט פלט Input-Output Devices, Controllers, and I/O Architectures ניהול ציוד ה יקפי INTERRUPTS שא ול ק ו בל מערכ ו ת מחש ב י ם ארכיטקטורה של קלט/פלט, מערכות ובקרים שאול קובל מערכות - Computers - Interrupt Controller Saul Coval CPU M Interrupt M OpSys Keyboard controller Message to application Application OpSys Special memory location M Interrupt CPU Decides which app (window) was accessed sends a message to that window Adds letter M to Video RAM Adds letter M to RAM Tells OpSys to display M Why are interrupts important Interrupts let you use the operating system (run your programs, manage your files, access your peripherals etc.) Interrupts help peripherals talk to your microprocessor Interrupts help you measure time and control the timing of certain tasks in your microprocessors Slide Slide Interrupts from a pedagogical perspective By learning interrupts you learn important concepts such as: Concurrency: how your processor manages to service interrupts while your program doesn t know anything about them and how multiple interrupts are serviced at the same time Preemptability and priorities, how can a low prioritytask be preempted by a high-priority task Scheduling: how can we assure that both low and high-priority tasks get the service they deserve from the processor Slide The INT and IRET instructions Syntax: INT imm imm is an interrupt vector from 0 to INT does the following: Pushes flag register (pushf) Pushes return and Far jumps to [0000:(*imm)] Usually clears the interrupt flag disabling the interrupt system IRET is to INT what RET is to CALL Pops flag register Performs a far return Slide

2 PIC - /Jan/00 Things to notice The interrupt vector table is just a big permanently located jump table The values of the jump table are pointers to code provided by bios, hardware, the operating system or YOU! Interrupt service routines preserve the flags the state of the microprocessor before the INT should be completely unaltered by the ISR and your program must return to normal operation. Hardware interrupts Alert the processor of some hardware situation that needs the processor s attention A key has been pressed A timer has expired A network packet has arrived Same software calling protocol Additional level of complexity with the interrupt call not coming from your program code Can happen at any time during the execution of your program, invocations of ISRs for hardware interrupts are asynchronous Slide Slide The 0x interrupt interface It is not that simple 0x processor INT Request (INTR) INT Acknowledge (INTA) Data bus Device generates request signal Device supplies interrupt vector number on data bus Processor completes the execution of current instruction and executes ISR corresponding to the interrupt vector number on the data bus ISR upon completion acknowledges the interrupt by asserting the INTA signal Some device Slide What if we want to connect more than one devices to the processor? What happens if multiple devices generate multiple interrupts at the same time? We need a way to share the two interrupt lines among multiple devices Programmable Interrupt Controller The PIC operates as an arbiter for interrupts triggered by multiple devices One serves up to devices, but multiple chips can be cascaded to serve up to devices Slide 0 The PIC Interrupt vectors and the PIC PIC 0 INTR INTA INT# Interrupt outputs from peripheral devices 0x Master-Slave Configuration 0x Base vector is 0h Master INTR 0 IRQ0 IRQ IRQ IRQ IRQ IRQ IRQ Slave INTR 0 Base vector is h IRQ IRQ IRQ0 IRQ IRQ IRQ IRQ IRQ Slide Slide

3 PIC - /Jan/00 The PIC PIC is very complex to program, fortunately the BIOS does most of the work needed Programmed with the I/O address 0h-h (master) and 0A0h-0Ah (slave) I/O instructions yet to be discussed in reads from an I/O address out writes to an I/O address Consider them as two registers the status register and the interrupt mask register The PIC The mask register is addressed from h It lets you enable/disable specific hardware interrupts Counterintuitive: a 0 ENABLES an interrupt and a DISABLES the interrupt Never load a value immediately to the mask register Always read the previous value and use and/or instructions to set the new mask in al, h ; this one reads the value of the mask register and al, 0efh ; this zeroes out bit i.e. IRQ out h, al ; this actually disables the interrupt in IRQ Slide Slide The PIC When an interrupt occurs and the processor starts executing the ISR all further interrupts from the same device are blocked until the ISR issues an end of interrupt instruction mov al, 0h out 0h, al You must end exactly one interrupt! Not sending one will block all interrupts from the save device Sending two or more means that you might accidentally acknowledge the end of a pending interrupt! Two more registers track pending interrupts received at the PIC and interrupt priorities You must be careful when you re patching existing ISR s (because the end instruction sequence may already be included in the ISR) The PIC IRQ mapping Interrupt vectors through 0Fh map to IRQ0- IRQ Interrupt vectors 0h-h map to IRQ-IRQ Slide Slide Typical IRQ assignments IRQ 0: Timer (triggered./second) IRQ : Keyboard (keypress) IRQ : Slave PIC IRQ : Serial Ports (Modem, network) IRQ : Sound card IRQ : Floppy (read/write completed) IRQ : Real-time Clock IRQ : Mouse IRQ : Math Co-Processor IRQ : IDE Hard-Drive Controller Interrupt priority Lower interrupt vectors have higher priority Lower priority can t interrupt higher priority Higher priority can interrupt lower priority ISR for INT h is running Computer gets request from device attached to IRQ (INT h) INT h procedure must finish before IRQ device can be serviced ISR for INT h is running Computer gets request from Timer 0 IRQ0 (INT h) Code for INT h gets interrupted, ISR for timer runs immediately, INTh finishes afterwards Slide Slide

4 PIC - /Jan/00 Priority in the supports several priority schemes On PC s the uses the simplest form of fixed priorities Each IRQ has a fixed priority Lower IRQs has higher priority The timer interrupt (IRQ0) has lower priority than any other IRQ If you really need higher priority than the timer (e.g. connecting a nuclear reactor to your microprocessor) it is possible to use a NMI (non-maskable interrupt) NMI has the highest priority among all hardware interrupts and cannot be disabled by the program Interrupt enabling/disabling You can enable/disable all maskable hardware interrupts The CLI instruction disables all maskable hardware interrupts The STI instruction enables all maskable hardware interrupts Be very careful if you ever need to use them Many deadlock scenarios! Slide Slide 0 The ugly details ISRs for hardware interrupts clear the interrupt flag at the beginning to disable interrupts. They may include a STI instruction if they want to enable interrupts before they finish It s all about performance! Keeping interrupts blocked for long is a BAD IDEA ISRs for software interrupts do not disallow hardware interrupts automatically at the beginning. If an ISR for a software interrupt needs to do that it must issue a CLI instruction This is what most ISRs do Again for the sake of performance a STI instruction must be issued as soon as possible Note that when interrupts are enabled the priority rule applies The CLI works only for maskable hardware interrupts Code enclosed between CLI/SCI is often called a critical section, an uninterruptible piece of code Slide Is there a way out of this mess? In many critical section situations (e.g. patching the interrupt vector tables) DOS helps us ensure the required atomicity Convenient calls for Safely getting the value of the interrupt vector from the interrupt vector table Safely storing a new value to the interrupt vector table (patching the interrupt vector table) In all difficult situations always examine what if scenarios What if a hardware interrupt occurs at different points of our ISR? Identify the points that need to be protected and protect them with CLI/STI Slide Servicing a hardware interrupt Complete current instruction Preserve current context PUSHF Store flags to stack Clear Trap Flag (TF) & Interrupt Flag (IF) Store return address to stack PUSH, PUSH Identify Source Read PIC status register Determine which device (N) triggered the interrupt Activate ISR Use N to index vector table Read / from table Jump to instruction Execute ISR usually the handler immediately re-enables the interrupt system (to allow higher priority interrupts to occur) (STI instruction) process the interrupt Indicate End-Of-Interrupt (EOI) to PIC mov al, 0h out 0h, al Return (IRET) POP (Far Return) POP POPF (Restore Flags) Interrupt service routines Reasons for writing your own ISR s to override the default ISR for internal hardware interrupts (e.g., division by zero need not terminate the program) to chain your own ISR onto the default system ISR for a hardware device, so that both the system s actions and your own will occur on an interrupt (e.g., clocktick interrupt, measure elapsed time) to service interrupts not supported by the default device drivers (a new hardware device for which you may be writing a driver) to provide communication between a program that terminates and stays resident (TSR) and other application software (maintain your ISRs) Slide Slide

5 PIC - /Jan/00 Impact of interrupts on performance The frequency of occurrence and the latency of the ISR determine the impact of servicing interrupts to your program The latency of the ISR is non-negligible! You may not notice it but you may be interrupted several times while executing your program. The good thing is that you don t notice it! Always remember: When the processor starts executing an ISR there might be other ISRs executing already Your ISR may be interrupted by a higher-priority interrupt Many devices expect low latency from your ISR (imagine what happens if you hit a key in the keyboard and wait for a minute!) Even those devices with high latencies (e.g. the disk) are not allowed to block other activity in the processor for long Bottom line YOUR INTERRUPT SERVICE ROUTINES MUST BE SHORT AND ACHIEVE THEIR PURPOSE WITH THE MAXIMUM EFFICIENCY! NEVER BLOCK THE SYSTEM WITH YOUR ISRs Slide Interrupt Service Routines ISRs are meant to be short keep the time that interrupts are disabled and the total length of the service routine to an absolute minimum remember after interrupts are re-enabled (STI instruction), interrupts of the same or lower priority remain blocked if the interrupt was received through the A PIC ISRs can be interrupted ISRs must be in memory Option : Redefine interrupt only while your program is running the default ISR will be restored when the executing program terminates Option : Use DOS Terminate-and-Stay-Resident (TSR) command to load and leave program code permanently in memory Slide Interrupt Driven I/O Consider an I/O operation, where the CPU constantly tests a port (e.g., keyboard) to see if data is available CPU polls the port if it has data available or can accept data Polled I/O is inherently inefficient Wastes CPU cycles until event occurs Analogy: Checking your watch every 0 seconds until your popcorn is done, or standing at the door until someone comes by Solution is to provide interrupt driven I/O Perform regular work until an event occurs Process event when it happens, then resume normal activities Analogy: Alarm clock, doorbell, telephone ring Slide VCC to CPU INTRQ from CPU INTA 0 Data Bus Master D0 IR0 D IR 0 D IR D IR D IR D IR D IR D IR A0 WR SP/EN CAS0 INT CAS INTA CAS A 0 Slave D0 D D D D D D D A0 WR SP/EN INT INTA A IR0 IR IR IR IR IR IR IR CAS0 CAS CAS 0 0 Master D0 D D D D D D D A0 WR SP/EN INT INTA A IR0 IR IR IR IR IR IR IR CAS0 CAS CAS 0 Address Bus Slide Slide 0

6 PIC - /Jan/00 0 Slave D0 D D D D D D D A0 WR SP/EN INT INTA A IR0 IR IR IR IR IR IR IR CAS0 CAS CAS 0 I/O Addressing Mode On CPU Chip IRQ IRQ IRQ Parallel Port Card Address Bus BC F F Data Bus Serial Port Card UART Serial Port Card UART Slide Slide Interrupts and our everyday lives We will spend at least two lectures to explain how to measure and track time in your microprocessor and you will be wondering why don t we just look at our watches But we will also learn that looking at your watch all the time is not a good thing to do, especially if you re a microprocessor We all have priorities E.g. you do your ECE homework and your girlfriend/boyfriend calls, there s a high-priority interrupt While you talk to your girlfriend/boyfriend you get another incoming call from your mom, there s an interrupt that you decide how to handle High priority: put the girlfriend/boyfriend on hold Low priority: put your mom on hold or don t even bother to switch to the other line Slide Interrupts seriously defined Triggers that cause the CPU to perform various tasks on demand Three types: Software interrupts initiated by the INT instruction in your program Hardware interrupts initiated by peripheral hardware Exceptions occur in response to error states in the processor or during debugging (trace, breakpoints etc.) Regardless of source, they are handled the same Each interrupt has a unique interrupt number from 0 to. These are called interrupt vectors. For each interrupt vector, there is an entry in the interrupt vector table. The interrupt vector table is simply a jump table containing Slide segment:offset addresses of procedures to handle each interrupt Interrupt vectors The first 0 bytes of memory (addresses FF) always contain the interrupt vector table. Always. Never anything else. Each of the vectors requires four Memory address (hex) bytes two for segment, two for offset 00FC * x INT INT x INT INT INT 0 Software interrupts Essentially function calls using a different instruction to do the calling and different conventions Software interrupts give you access to built-in code in the BIOS, the operating system, or peripheral devices Software interrupts are triggered with the INT instruction Slide Slide

PIC - /Jan/00 U 0 WR WR A0 A A D0 D D D D D D D ADS RESET XTAL/CLK XTAL RCLK 0 OUT OUT INT TXD RTS DTR RXD DCD DSR CTS RI OUT DDIS NC BAUDOUT 0 0 0 0 Slide Slide End-to to-end Modem-based DC

transmission protocols, RS-, RS, RS-, RS-, RS-, RS-0, V. 0 0 PC Parallel transmission Physical interfaces vs.

7 PIC - /Jan/00 U 0 WR WR A0 A A D0 D D D D D D D ADS RESET XTAL/CLK XTAL RCLK 0 OUT OUT INT TXD RTS DTR RXD DCD DSR CTS RI OUT DDIS NC BAUDOUT Slide Slide End-to to-end Modem-based DC PROCESSES PROTOCOLS AND STANDAS Serial transmission standards Computer to Modem Character encoding Serial transmission ASCII, EBCDIC, UNICODE, ISO0 Physical interfaces vs. transmission protocols, RS-, RS, RS-, RS-, RS-, RS-0, V. 0 0 PC Parallel transmission Physical interfaces vs. transmission protocols Centronics interface, DB- interface Pin Number Signal Designation Pin Number Signal Designation Pin Number Signal Designation Within the Modem Serial/parallel conversion Data transmission Modulation/Demodulation Universal Asynchronous Receiver/Transmitter (UART) Digital vs. analog transmission Carrier wave characteristics amplitude, frequency, phase Protective ground Transmit data Receive data Request to send Secondary transmit data Transmit clock (DCE) Secondary receive data Receiver clock Carrier detect Receive data Transmit data Data terminal ready Modem Modulation techniques Amplitude modulation, frequency shift keying, phase shift keying, quadrature amplitude modulation Clear to send Data set ready Receiver dibit clock Secondary request to send Protective ground Data set ready Digital encoding and transmission Manchester encoding, NRZ-L, BZ synchronous transmission, asynchronous transmission Signal ground Carrier detect 0 Data terminal ready Signal quality detector Request to send Clear to send Modem to Phone Services RJ- phone jack Phone network Phone service transmission Phone services alternatives Two-wire vs. Four-wire, full-duplex vs. half-duplex, echo cancellation Analog vs. digittal services, dial-up vs. leased line services, bandwidth differentiation of services 0 Positive DC test voltage Negative DC test voltage unassigned Ring indicator Data signal rate selector Transmit clock (DTE) Ring indicator RJ- phone jack Secondary carrier detect Busy Modem PC Secondary clear to send Slide Slide 0 Pin Signa l CD TD DTR SG DSR RTS CTS RI Description Carrier Detect Receive Data Transmit Data Data Terminal Ready Signal Ground Data Set Ready Request to Send Clear to Send Ring Indicator I/O In In Out Out - In Out In In transmitting modem PSTN Error check Calculated calculated error check based on and actual actual data data transmitted GOLDMAN: DATACOMM FIG. 0-0 receiving modem Error check Recalculated recalculated error check based on compared to received transmitted error data check Slide Slide

8 PIC - /Jan/00 Serial Port Resources I/O addresses and IRQ Com Port I/O Address IRQ COM F-FF COM F-FF COM E-EF COM E-EF Slide Slide Slide Slide Slide Slide

PIC - /Jan/00 Interrupts Hardware interrupts Defined by CPU Defined by board-level architecture Software interrupts Convenient mechanism to call Operating System defined by software

Offset Segment Offset Segment IVT Format Interrupt 0 Interrupt LSB MSB LSB MSB Memory Address (hex) ISR address Interrupt Function Pointer Given a Vector, where is the ISR address

9 PIC - /Jan/00 Interrupts Hardware interrupts Defined by CPU Defined by board-level architecture Software interrupts Convenient mechanism to call Operating System defined by software Exceptions in response to a condition encountered during execution of an instruction Slide Slide 0 Slide Slide 0000: : : : : : : :000 Offset Segment Offset Segment IVT Format Interrupt 0 Interrupt LSB MSB LSB MSB Memory Address (hex) ISR address Interrupt Function Pointer Given a Vector, where is the ISR address stored in memory? 00FC INT * x INT x 0000 INT 0000 INT 0000:0fc 0000:0fd 0000:0fe 0000:0ff Offset Segment Interrupt Example: int h Offset = ( ) = = 00dh INT 0 Slide Slide

10 PIC - /Jan/00 Interrupt Vector Assignments Type Function Comment 0 Divide Error Processor - zero or overflow Single Step (DEBUG) Processor - TF= Nonmaskable Interrupt Pin Processor - NMI Signal Breakpoint Processor - Similar to Sing Step Arithmetic Overflow Processor - into Print Screen Key BIOS - Key Depressed Invalid Opcode Processor - Invalid Opcode Coprocessor Not Present Processor - no FPU Time Signal BIOS - From RT Chip (AT - IRQ0) Keyboard Service BIOS - Gen Service (AT - IRQ) A - F Originally Bus Ops (IBM PC) BIOS - (AT - IRQ-) 0 Video Service Request BIOS - Accesses Video Driver Equipment Check BIOS - Diagnostic Memory Size BIOS - DOS Memory Disk Service Request BIOS - Accesses Disk Driver Serial Port Service Request BIOS - Accesses Serial Port Drvr Miscellaneous BIOS - Cassette, etc. Keyboard Service Request BIOS - Accesses KB Driver Interrupt Vector Assignments (cont) Type Function Comment Parallel Port LPT Service BIOS - Printer Driver ROM BASIC BIOS - BASIC Interpreter in ROM Reboot BIOS - Bootstrap A Clock Service BIOS - Time of Day from BIOS B Control-Break Handler BIOS - Keyboard Break C User Timer Service BIOS - Timer Tick D Pointer to Video Parm Table BIOS - Video Initialization E Pointer to Disk Parm Table BIOS - Disk Subsystem Init. F Pointer to Graphics Fonts BIOS - CGA Graphics Fonts 0 Program Terminate DOS - Clear Memory, etc. Function Call DOS - Transfer Control Terminate Address DOS - program Terminate handler Control-C Handler DOS - For OS Use Fatal Error Handler DOS - Critical Error Absolute Disk Read DOS - Disk Read Absolute Disk Write DOS - Disk Write Terminate DOS - TSR Usage Idle Signal DOS - Idle F Print Spool DOS - Cassette, etc. 0- Hardware Interrupts in AT Bios DOS - (AT - IRQs -) Slide Slide IBM-AT ( AT IRQ Definitions AT (Advanced Technology) - Intel 0) Name Interrupt Vector Priority Description NMI 0 Memory Parity Error IRQ0 0 Timer (Intel Chip ms intervals) IRQ 0 Keyboard IRQ 0A PIC Slave or EGA/VGA Vert. Retrace IRQ 0B Serial Port (COM or COM) IRQ 0C Serial Port (COM or COM) IRQ 0D Fixed Disk or LPT Request IRQ 0E Floppy Disk Driver IRQ 0F LPT Request IRQ 0 CMOS Real-Time Clock (RT Chip) IRQ Re-directed to IRQ IRQ0 RESERVED IRQ RESERVED IRQ Mouse or other IRQ 0 Math Coprocessor (NPX) IRQ Hard Disk IRQ RESERVED Software Interrupts BIOS Calls Keyboard -- INT H Video I/O -- INT 0H Serial I/O -- INT H Printer I/O -- INT H Time of day -- INT AH Timer tick -- INT CH DOS Calls Function request -- INT H Slide Slide Offset Address Type No. Interrupt Processing SP L H L H Status L Status H Interrupt Vector Table C C C C C 0 0 A B C 0 Division by zero Single Stepping NMI Interrupt -byte INT (opcode = CC) Signed overflow Print Screen Video I/O Equipment Check Memory Size Diskette I/O Serial Communication I/O Cassette I/O Keyboard I/O Printer I/O Cassette BASIC Bootstrap Time of Day Keyboard Break Timer Tick Program Terminate Function Request Terminate Address Ctrl-Break Exit Address BIOS DOS Slide F FE FC FF Slide 0 0

11 PIC - /Jan/00 Interrupt service routines end with an IRET instruction that pops the following values off the stack. SP L H L H Status L Status H Interrupt Vector Table Offset address C 00 0 Type number 0 Division by zero Single Stepping NMI Interrupt -Byte INT (opcode = CC) Signed overflow (INTO) Print screen Slide Slide The Status Register Time of Day Interrupt: INT AH O D I T S Z - A - P - C Overflow Direction Interrupt enable Trap Sign Zero Parity Auxiliary Carry Carry AH = 0 AH = Read the -bit counter clock setting Output: CX = high word of count DX = low word of count AL = 0 if count has not exceeded hours since last read = if hours has passed Set the -bit counter clock Input: CX = high word of count DX = low word of count Slide Slide Hardware Interrupts Nonmaskable Interrupt, NMI ) the status register, code segment register (), and instruction pointer () are pushed on the stack (see Figure.). ) the program jumps to : where the instruction pointer is stored in locations 0000: :000 and the code segment is stored in locations 0000:000A 0000:000B. Thus a non-maskable interrupt is a Type interrupt. (see Figure. in Chapter ). SP L H Table. PC Hardware Interrupts Interrupt Interrupt Vector Name Type No. Hex Offset Address 0 Timer Tick Keyboard A Unused B C Reserved for COM Serial I/O C 0 Reserved for COM Serial I/O D Unused E Disk I/O F C Reserved for Printer L H Status L Status H Slide Slide

12 PIC - /Jan/00 Interrupt Vector Table RESET 0 0C A Keyboard I/O Printer I/O Cassette BASIC Bootstrap Time of Day Set Status,, DS, SS, and ES to 0000H Set to FFFFh Execution begins at FFFF:0000 = FFFF0 (on Pentium, execution begins in real mode at FFFFFFF0) 0C B Keyboard Break 00 C Timer Tick Slide Slide Table. PC Hardware Interrupts Interrupt Interrupt Vector Hex Name Type No. Offset Address 0 Timer Tick Keyboard A Unused B C Reserved for COM Serial I/O C 0 Reserved for COM Serial I/O D Unused E Disk I/O F C Reserved for Printer Any Questions Slide Slide 0 Any Questions Any Questions Slide Slide

8086 Interrupts and Interrupt Responses:

UNIT-III PART -A INTERRUPTS AND PROGRAMMABLE INTERRUPT CONTROLLERS Contents at a glance: 8086 Interrupts and Interrupt Responses Introduction to DOS and BIOS interrupts 8259A Priority Interrupt Controller